1. Field of the Invention
The present invention relates to the storage of information by altering the operational characteristics of a transistor within an array of memory transistors and, more particularly, to a non-volatile memory such as a read only memory (ROM).
2. Description of the Related Art
Conventional read only memories (ROMs) consist of an array of field effect transistors, with each memory cell including a single field effect device. Each of the field effect transistors can be formed so as to have one of two predetermined values of a particular characteristic of the transistor. The selectable transistor characteristic might, for example, be the threshold voltage of the transistor. Implanting impurities into the channel region of the transistor might cause the transistor to have a low threshold voltage so that the transistor is turned on by application of V.sub.CC to the gate of the transistor. Transistors formed without implanting impurities into the channel might have a high threshold voltage and the transistor is not turned on by application of V.sub.CC to the gate of the transistor. Alternately, transistors formed without implanting impurities into the channel region may have a low threshold voltage, and transistors having implanted channel regions may have high threshold voltages. Binary data can then be stored in the memory by selectively implanting impurities into the channels of the transistors, with transistors having impurities implanted into the channel region storing a logical zero and transistors having no impurities implanted into the channel region storing a logical one. Of course, the opposite assignment of logical values is also known.
There is a constant need to provide non-volatile memories which can be rapidly programmed to provide quick turn around time memories for a variety of applications. ROMs programmed by implanting impurities into the channel of memory transistors are programmed early in the manufacturing process and must undergo a number of further processing steps before the ROM is ready to be shipped. Such ROMs have undesirably long turn around times. Non-volatile memories such as flash memories can be programmed after all processing is done on the device and so have short turn around times. Flash memories, however, are unacceptably expensive in comparison to mask ROMs. It is thus desirable to provide an inexpensive non-volatile memory having a shorter turn around time.
Recent memory designs are near the limits of semiconductor processing technology in that further reductions in the size of devices in memories will require significant improvements in processing technology. For example, programming ROMs by the selective implantation of impurities into the channels of transistors relies on a careful mask alignment to define the implantation mask. For 0.5 .mu.m design rules, such as are implemented in some current memory designs, alignment of the implantation mask is a time consuming and error prone process which increases the cost of the ROM and undesirably reduces yield. Device design considerations also limit the extent to which the information storage density of conventional ROMs can be increased. For example, conventional ROMs contact the source and drain regions of a row of transistors using buried N.sup.+ lines. For reduced design rules in which these lines are made smaller, the resistance of these buried N.sup.+ lines inevitably increases because it is not possible to adopt higher doping levels without increasing dopant diffusion into the channel regions and into adjacent device regions. As the resistance of the buried N.sup.+ lines increases, the RC time constant of the lines increases and increases the time required to read information out of the ROM.
Accordingly, it is desirable to provide an inexpensive non-volatile memory compatible with reduced dimension design rules that is readily manufacturable and which provides improved memory storage density.